In recent years, as a successor candidate of a semiconductor memory device, a resistance change memory which uses, as a memory cell, a variable resistance element whose resistance varies based on a voltage to be applied, for example, a resistive random access memory (ReRAM) has been attracting attention (for example, see Jpn. Pat. Appln. KOKAI Publication No. 2008-287827).
In a resistance change memory, it has been found that a state of a memory cell changes depending on an application of a minute voltage. Since the memory cell cannot hold its previous state even though a minute voltage is applied, a serious problem on reliability is posed.
In this case, in the resistance change memory, after an operation such as a read operation or a state change operation, an interconnection connected to the memory cell may be unnecessarily electrically charged. In this case, unnecessary voltage stress acts on the memory cell when a power supply is turned on/off or a next operation is executed, and the state of the memory cell may be changed.
As a transistor which drives a normal voltage, a p-channel transistor may be used. However, in this case, the p-channel transistor is turned on in a power-off state, electric charge accumulated in the interconnection or the like is discharged, and voltage stress may disadvantageously act on the memory cell.